1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a liquid crystal display device and a testing method thereof that is capable of accurately detecting a point defect existing in a liquid crystal display panel.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls light transmissivities of liquid crystal cells in response to a video signal to thereby display a picture. An active matrix LCD in which a switching device is provided for each liquid crystal cell is suitable for displaying a moving picture. The active matrix LCD mainly uses a thin film transistor (TFT) as the switching device. Since such an active matrix LCD can be made into a smaller device in size than the existent Brown tube, it has been widely used for personal computers or notebook computers, as well as office automation equipment such as copy machines, etc., and portable equipment such as cellular phones and pagers, etc.
A method of fabricating such an active matrix LCD may be divided into substrate cleaning, substrate patterning, alignment film formation, substrate adhesion/liquid crystal injection, packaging and test processes.
In the substrate cleaning process, a cleaner removes any alien substance on the substrates before and after patterning the upper and lower substrate.
The substrate patterning process is divided into a step of patterning the upper substrate and a step of patterning the lower substrate. The upper substrate is typically provided with color filters, a common electrode and black matrices, etc. The lower substrate is provided with signal wires such as data lines and gate lines, etc. A thin film transistor (TFT) is arranged at each intersection between the data lines and the gate lines. A pixel electrode is formed at each pixel area between the data lines and the gate lines.
In the substrate adhesion/liquid crystal injection process, a step of coating an alignment film on the lower substrate and rubbing it is sequentially followed by a step of adhering the upper substrate to the lower substrate using a seal, a liquid crystal injection step, and an injection hole sealing step.
In the packaging process, a tape carrier package (TCP) mounted with integrated circuits such as a gate drive integrated circuit and a data driver integrated circuit, etc. is connected to a pad portion on the substrate. In the meantime, when the driver circuit is mounted by a chip on glass (COG) system, a circuit pattern is directly mounted onto a polysilicon substrate in said substrate patterning process.
The LCD device may have a defect caused by a process error in its fabrication process, a deterioration of the TFT characteristic, an interference between circuits or a signal delay, etc. upon its driving. In order to detect such a defect, the fabrication process of the LCD device includes a testing process.
In a conventional testing process as shown in FIG. 1, a liquid crystal display panel 8 is scanned from the top to the bottom thereof, that is, in a forward direction to display gray patterns (RGB) for testing on the screen.
The liquid crystal display panel 8 is provided with m gate lines G1, G2, . . . , Gm and n data lines D1, D2, . . . , Dn crossing each other. A TFT 5 is formed at each intersection between the m gate lines G1, G2, . . . , Gm and the n data lines D1, D2, . . . , Dn. The TFT 5 is connected to a pixel electrode to drive a liquid crystal pixel cell 6. Tape carrier packages (TCPs) 1 and 4 are attached to pads of the gate lines G1, G2, . . . , Gm, and the data lines D1, D2, . . . , Dn of the liquid crystal display panel 8 respectively. The TCPs 1 and 4 have mounted thereon integrated circuits (IC's) 2 and 3.
The gate driving TCP 1 and the data driving TCP 4 are controlled by a controller board 7. The data driving TCP 4 is synchronized with a dot clock Dclk from the controller board 7 to apply a gray test pattern for each one line to the data lines D1, D2, . . . , Dn. The gate driving TCP 1 is connected to the controller board 7 to scan the gate lines G1, G2, . . . , Gm sequentially from the first gate line G1 until the mth gate line Gm under control of the controller board 7.
The controller board 7 generates signals for controlling the gate driver IC 2 mounted on the gate driving TCP 1, that is, a gate shift clock GSC, a gate output enable signal GOE and a gate start pulse GSP. The gate shift clock GSC controls a time at which the gate of the TFT 5 is turned on or off. The gate output enable signal GOE is a signal controlling the output of the gate driver IC 2. The gate start pulse GSP is a signal indicating the drive timing of the first scanned gate line of the screen, that is, the first gate line G1 in one vertical synchronous signal.
When the testing gray pattern data RGB is being supplied, via the data driver IC 3, to the data lines D1, D2, . . . , Dn, the controller board 7 controls the gate driver IC 2 to sequentially scan from the first gate line G1 to the mth gate line Gm. At this time, the gate start pulse GSP generated from the controller board 7 is applied to a stage of a shift resister connected to the first gate line G1 and then is sequentially applied to the low-order gate driver ICs 2. In other words, the gate start pulse GSP is applied to the gate driver IC 2 connected to the first gate line G1 and then is eventually applied to the gate driver IC 2 connected to the mth gate line Gm (GSP_L→GSP_H). If the gate lines G1, G2, . . . , Gm are sequentially driven, then a channel is defined in each of the corresponding TFTs 5, to thereby supply data on the data lines D1, D2, . . . , Dn to the liquid crystal pixel cells. Then, the gray test pattern is displayed on the screen. The testing process operator observes the screen using a microscope to judge a defect of the liquid crystal pixel cell.
However, according to the conventional testing process, since an electric field applied to the liquid crystal pixel cell 6 is small, the brightness of the displayed test picture is not high. For this reason, it is impossible to find a point defect of the liquid crystal display panel 8, particularly to accurately find a point defect existing at the edge of the liquid crystal display panel 8. For instance, if a test data voltage of 6V is applied to the liquid crystal pixel cell 6 when a gate low voltage and a gate high voltage are −5V and 20V, respectively, then a voltage of 11V is charged in the liquid crystal pixel cell 6 at a positive electric field because the gate low voltage Vgl is −5V. In this case, it becomes difficult to find point defects existing in the edge areas 8A and 8B of the liquid crystal display panel 8 as shown in FIG. 2.